//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// Clocked RAM Cell for M8051W/EW Program Memory
// 
// $Log: cpram.v,v $
// Revision 1.2  2002/01/09
// Final testbench changes for version2
//
// Revision 1.1  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.1  2001/11/14
// First EW checkin
//
// Revision 1.3  2000/03/06
// Revised configuration scheme
//
// Revision 1.2  2000/02/05
// Name change from m8051e to m8051ewarp
//
// Revision 1.1.1.1  1999/10/28
// "initialization and source check-in for m8051e"
//
//
////////////////////////////////////////////////////////////////////////////////
//
// Purpose      :       Configurable clocked memory cell for modelling
//              :       the program store used by the M8051W/EW Soft Core.
//
////////////////////////////////////////////////////////////////////////////////

`include "m8051w_tb_cfg.v"

module cpram (out_data, in_data, address, ncs, noe, nwe, clk);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //

parameter [89:1] IMAGE_NAME = "program.rom";
output [7:0] out_data;
input  [7:0] in_data;
input  [(`RomALines -1):0] address;
input  ncs;
input  noe;
input  nwe;
input  clk;

reg [7:0]  MemArray [0:(`RomSize - 1)];
reg [`RomALines-1:0]  reg_address;
reg [7:0]  read_data;
wire [7:0] out_data;
wire       noe_int;
integer    i;

// Load an image into the array at simulator start time
initial
begin
  $display("Reading image from %s into cpram", IMAGE_NAME);
  //for (i = 0; i < `RomSize; i = i +1)
  for (i = 0; i < `RomSize; i = i+3)
    //MemArray[i] = 8'hff; // Old style of initialisation
  begin  // Fills the memory with the LJMP 0000h instruction
    if (i     < `RomSize) MemArray[i]   = 8'h02; // LJMP
    if ((i+1) < `RomSize) MemArray[i+1] = 8'h00; // 00
    if ((i+2) < `RomSize) MemArray[i+2] = 8'h00; // 00
  end  
  $readmemh(IMAGE_NAME, MemArray);
end

// Model clocked array access
always @(posedge clk)
begin
  if (~ncs) reg_address <= address;
  if (~nwe) begin
     if (^address === 1'bx) begin
      $display("Bus Error:   At time %t, CPRAM address indeterminate during write: %b",
               $time, address);
      for (i = 0; i < `RomSize; i = i +1) MemArray[i] = 8'hxx;
      end
    else
      MemArray[address] <= in_data;
  end
end

// Model asynchronous memory core
always @(reg_address)
begin
    read_data <= #(`Thclk * 0.2) `BadData;
    read_data <= #`Tromacc MemArray[address];
end

// Model tristate enable delay
assign #`Tromoe noe_int = noe;

// Simple tri-state driver
assign out_data = ~noe_int? read_data: 8'hzz;

endmodule
